1. Field of the Invention
The present invention relates to a data processing apparatus, a control method therefor, and a non-transitory computer-readable storage medium and, more particularly, to a data processing apparatus for executing data processing (so-called cascade processing) in which data processing is repeatedly executed for a plurality of input data, and it is determined based on the processing result of the preceding stage whether processing of the succeeding stage is to be executed, a control method for a data processing apparatus, and a non-transitory computer-readable storage medium.
2. Description of the Related Art
There has been conventionally proposed a technique of detecting a specific subject such as a person or face in an input image and executing processing suitable for the detected subject in a digital camera or printer. As an example of the processing of detecting a specific subject, there is face detection processing for executing skin color correction processing for a face.
There have been proposed various methods as face detection processing, such as P. Viola and M. Jones, “Robust Real-time Object Detection”, SECOND INTERNATIONAL WORKSHOP ON STATISTICAL AND COMPUTATIONAL THEORIES OF VISION, Jul. 13, 2001 (to be referred to as “Viola & Jones method” hereinafter) and a method of detecting a human face using the symmetric features of a human face, template matching, neural networks, and the like. In the Viola & Jones method, verification processing is executed based on a learning result by AdaBoost. This verification processing is cascade processing as follows. That is, as a result of certain verification processing, TRUE is output when next verification processing is to be executed and FALSE is output when next verification processing is not to be executed. When FALSE is output, the verification processing ends.
In such verification processing, to increase the processing speed while suppressing the circuit scale of an internal memory, a cache method or prefetch method (a method of preparing in advance parameters necessary for a next operation) is widely used as a conventional technique for shortening a processing waiting time required to load parameters such as dictionary data.
The cache method and prefetch method as conventional techniques for increasing the processing speed while suppressing the circuit scale of an internal memory have the following problems.
That is, in the cache method which deletes the oldest dictionary data when a shortage of a storage area occurs, if FALSE is output after steps the number of which is larger than that of parameter storage units are processed, it is always necessary to reload all dictionary data in next input data processing and it is, therefore, impossible to obtain the effects of the cache method at all.
On the other hand, in the prefetch method, dictionary data necessary for a next operation is predicted to be dictionary data for a next step, and is then prefetched. However, in recognition processing, the prediction may turn out to be wrong. In the prefetch method, therefore, corresponding processes are sequentially executed in the order of step numbers. In this case, for example, if dictionary data 3 is loaded during processing in step 2 and the result of the processing in step 2 is FALSE, the load operation of dictionary data 3 is in vain. Furthermore, dictionary data 1 necessary for a next operation is deleted and, therefore, it takes time to reload dictionary data 1.
The present invention has been made in consideration of the above problems. The present invention provides a technique of increasing the processing speed while suppressing the circuit scale of an internal memory.